The present invention relates to a semiconductor integrated circuit device including a memory circuit and a logic circuit and a method of testing the semiconductor integrated circuit device.
Recently, various types of semiconductor integrated circuit devices (hereinafter referred to as LSIs) with a variety of memory built-in structures have been put in practical use. For example, in order to attain a high speed data processing, a plurality of memories each with a small capacity are provided on the same substrate as data processing buffers, or a memory with a large capacity such a cache memory of a microprocessor is provided on the same substrate.
Therefore, not only increase of the scale of the LSI but also security for test coverage, decrease of an increasing test time, etc. in conducting a functional test of the LSI have become significant problems.
In general, an operation test of an internal combinational circuit including a logic circuit built in an LSI (namely, the so-called logic test) is carried out by supplying the LSI with a predetermined test vector for confirming the function of the LSI and by comparing an operational value in response to the test vector read from the LSI with an expected value. This is not, however, a very good method to secure the test coverage of the operation test with a small number of test vectors.
Accordingly, a flip-flop or the like built in an LSI is recently provided with a sequential circuit having a scan function, and a test by a scanning method using the sequential circuit has been occasionally adopted. The test by the scanning method (hereinafter referred to as the scan test) is described in, for example, "Digital Kairo No Kosho Shindan, vol. 1" by Kinoshita, et al., pp. 214-215, published by Kogaku Tosho K. K.). Furthermore, a memory test for a built-in memory in an LSI is carried out by conducting a data read/write test using a predetermined algorithm such as a marching algorithm and a checker algorithm.
However, the read/write test is not sufficient in the built-in memory. For example, even when the built-in memory has a memory cell structure of an SRAM base, there is possibility of occurrence of a production problem such as data disappearance due to a leakage current in a specific memory cell. Therefore, a test for securing data hold during a predetermined time period is required to be conducted. Specifically, in this data holding test, a predetermined data is previously written in a memory, no data is written in or read from the memory for a predetermined period of time, and it is checked whether or not the written data is held after the predetermined period of time. The data holding test requires a holding period of several tens through several hundreds ms (milliseconds) during which no memory access is executed. This period is much longer than a general operation time of an LSI of several through several tens ns (nanoseconds).
Now, a method of testing a conventional LSI will be described with reference to the accompanying drawing.
FIG. 8 is a circuit diagram of the conventional LSI. As is shown in FIG. 8, on a semiconductor substrate 100 are formed an image processor 110 for executing an image processing of data according to the MPEG standard and computer graphic (CG) data, a memory circuit unit 120 for storing image processed data, and a memory control unit 125 for controlling an input/output operation of the memory circuit unit 120. The image processor 110, the memory circuit unit 120 and the memory control unit 125 are respectively supplied with a clock signal 130 for synchronizing the input/output of data.
The image processor 110 includes scan-functioning flip-flops 111A and 111B having a scan path for the scan test, which is one of the operation tests for the image processor 110.
The memory circuit unit 120 includes a scan-functioning flip-flop 121a for synchronizing an internal data bus DIN on the basis of the clock signal 130, a scan-functioning flip-flop 121b for synchronizing an internal address bus AIN on the basis of the clock signal 130, a scan-functioning flip-flop 121c for synchronizing an internal control signal WR on the basis of the clock signal 130, and a memory core 123 for receiving a synchronous data signal 135, a synchronous address signal 136 and a synchronous memory control signal 137 and storing image processed data and the write/read operations thereof. In this circuit, the flip-flops 121a through 121c form a first scan path circuit 121.
In an LSI having a clock synchronous memory like this conventional LSI, the flip-flops 121a through 121c for synchronizing input data for the memory circuit unit 120 are provided with the scan function, so that a test data input from the memory control unit 125 to the first scan path circuit 121 can be subjected to the scan test by using a data path including testing selectors. Thus, the test coverage in a testable area 129 can be improved. Furthermore, since the test is batched, the management of the test coverage can be batched with regard to each test item. This leads to an advantage that fails in the memory circuit unit 120 and the memory control unit 125 can be distinguished from each other with ease. In addition, when the LSI does not have a single-chip structure, for example, when the memory circuit unit 120 and the memory control unit 125 are formed on the separate substrates, these substrates are connected with each other through a printed substrate. This leads to another advantage that these units can be tested separately from the memory core 123.
The memory circuit unit 120 is provided with a CS terminal 122 for receiving a chip select signal 132 from the memory control unit 125. At this point, the chip select signal 132 is used for decreasing an operational current by inhibiting the data read/write operation for a predetermined period of time, or in the case where the LSI adopts a bank memory with a large capacity by using plural memories each with a small capacity, the chip select signal 132 is used for making a selected bank memory alone accessible by inhibiting the read/write operation on other memories apart from the selected bank memory.
The memory control unit 125 includes a second scan path circuit 126 for conducting the scan test of the memory control unit 125 and a memory control circuit 127 for controlling the input/output operation of the memory circuit unit 120. The scan-functioning flip-flops 111A and 111B are connected with the second scan path circuit 126 in series through a scan path 131.
Between the memory circuit unit 120 and the memory control unit 125, selectors 128 are interposed, which are switched in accordance with a test mode signal 133 activated in conducting the read/write test of the memory circuit unit 120.
For the scan test in the memory circuit unit 120, a scan-in signal 131a is input to the flip-flop 121a, passes through the flip-flop 121b and enters the flip-flop 121c, which outputs a scan-out signal 131b. Thus, the scan test is conducted by forming the scan path 131.
The specific method of the scan test is described in the aforementioned publication by Kinoshita et al.
In conducting the read/write test of the memory in the memory circuit unit 120, the test mode signal 133 is activated. This activation keeps the chip select signal 132 always activated during the test of the memory circuit unit 120. While the chip select signal 132 is being activated, the read/write operation on the memory circuit unit 120 is enabled, and while the chip select signal 132 is being deactivated, the read/write operation on the memory circuit unit 120 is inhibited.
When the test mode signal 133 is deactivated as in the normal operation mode, the chip select signal 132 has a substantially undefined value because it depends upon a control output of the memory control unit 125. Specifically, in the normal operation mode, the chip select signal 132 is activated by the memory control unit 125 in the cases where current consumption excluding a stationary current is to be decreased by inhibiting an access to the memory and where an access to the bank memories apart from a selected bank memory is inhibited when the memory includes plural banks.
On the other hand, when the test mode signal 133 is activated, the selector 128 selects a test data bus TB, and a test data value is input to the memory circuit unit 120 through the internal data bus DIN of the memory circuit unit 120. As a result, the memory circuit unit 120 can be directly or indirectly accessed from the outside of the LSI. Therefore, a predetermined memory pattern is written in the memory circuit unit 120 by using the test data bus TB, a test address bus TA and a test memory control signal TC, and a read value of the test data output from a test output terminal is compared with an expected value. Thus, the read/write test of the memory circuit unit 120 is completed.
As described above, the read/write test is not sufficient for testing the memory circuit unit 120 but the data holding test is also required. The data holding test is significant for preventing the problem that stored data are disappeared before a defined data holding period elapses due to an abnormal leakage current and supply voltage dependency resulting from a defect caused in the manufacture of the memory.
However, according to the aforementioned method of testing the conventional LSI, a time period of several tens through several hundreds ms is required for the data holding test of the memory circuit unit 120. This time period is longer than time required for another test, whose basic operation cycle is (several ns through several tens ns).times.(the number of patterns). Therefore, most of time required for the test of the LSI should be spent for the data holding test.
Furthermore, during the scan test for testing the image processor 110 and the memory control unit 125 of the LSI, the flip-flops 121a through 121c are not controlled to have their contents retained at constant values, and hence the content of the memory core 123 cannot be guaranteed. Therefore, the time for the data holding test cannot be shared by the scan test. In addition, due to the high integration of the image processor 110 and the memory control unit 125, the scan test itself tends to require a longer test time.
In this manner, since the content of the memory cannot be controlled to be updated during the data holding test, the time required for testing the entire LSI is disadvantageously increased.